Towards a new quasigroup block cipher for a single-chip FPGA implementation

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In earlier work the authors reported on methods they investigated to implement quasigroup block encryption in hardware, with an emphasis on low cost. The aim was to design and deliver a hardware design solution that was inexpensive but did not sacrifice encryption security; the desired target for the design is low-bandwidth, low-cost areas such as Supervisory Control And Data Acquisition (SCADA) systems. Here the authors report on further refinements of this design with the aim of making a single-chip solution.

Original languageEnglish (US)
Title of host publication24th International Conference on Computer Communications and Networks, ICCCN 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479999644
DOIs
Publication statusPublished - Oct 2 2015
Event24th International Conference on Computer Communications and Networks, ICCCN 2015 - Las Vegas, United States
Duration: Aug 3 2015Aug 6 2015

Publication series

NameProceedings - International Conference on Computer Communications and Networks, ICCCN
Volume2015-October
ISSN (Print)1095-2055

Other

Other24th International Conference on Computer Communications and Networks, ICCCN 2015
CountryUnited States
CityLas Vegas
Period8/3/158/6/15

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Keywords

  • FPGA
  • Latin Squares
  • Quasigroup
  • SCADA

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

Cite this

Mahoney, W., & Parakh, A. (2015). Towards a new quasigroup block cipher for a single-chip FPGA implementation. In 24th International Conference on Computer Communications and Networks, ICCCN 2015 [7288479] (Proceedings - International Conference on Computer Communications and Networks, ICCCN; Vol. 2015-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCCN.2015.7288479