Structured bit-interleaved LDPC codes for MLC flash memory

Kathryn Haymaker, Christine A. Kelley

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

Due to a structural feature in the programming process of MLC (two bits per cell) and TLC (three bits per cell) flash memory, the majority of errors that occur are single-bit errors. Moreover, the voltages used to store the bits typically result in different bit error probabilities for the two or three types of bits. In this work we analyze binary regular LDPC codes in the standard bit-interleaved coded modulation implementation, assuming different probabilities on the bits, to determine what ratio of each type of bit should be connected at the check nodes to improve the decoding threshold. We then propose a construction of nonbinary LDPC codes using their binary images, resulting in check node types that come close to these optimal ratios.

Original languageEnglish (US)
Article number6804932
Pages (from-to)870-879
Number of pages10
JournalIEEE Journal on Selected Areas in Communications
Volume32
Issue number5
DOIs
StatePublished - May 2014

Fingerprint

Flash memory
Binary images
Decoding
Modulation
Electric potential

Keywords

  • Parity check codes
  • bipartite graph
  • iterative decoding

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Structured bit-interleaved LDPC codes for MLC flash memory. / Haymaker, Kathryn; Kelley, Christine A.

In: IEEE Journal on Selected Areas in Communications, Vol. 32, No. 5, 6804932, 05.2014, p. 870-879.

Research output: Contribution to journalArticle

@article{c6f90a438da94eaa8eed4f46eea55df0,
title = "Structured bit-interleaved LDPC codes for MLC flash memory",
abstract = "Due to a structural feature in the programming process of MLC (two bits per cell) and TLC (three bits per cell) flash memory, the majority of errors that occur are single-bit errors. Moreover, the voltages used to store the bits typically result in different bit error probabilities for the two or three types of bits. In this work we analyze binary regular LDPC codes in the standard bit-interleaved coded modulation implementation, assuming different probabilities on the bits, to determine what ratio of each type of bit should be connected at the check nodes to improve the decoding threshold. We then propose a construction of nonbinary LDPC codes using their binary images, resulting in check node types that come close to these optimal ratios.",
keywords = "Parity check codes, bipartite graph, iterative decoding",
author = "Kathryn Haymaker and Kelley, {Christine A.}",
year = "2014",
month = "5",
doi = "10.1109/JSAC.2014.140507",
language = "English (US)",
volume = "32",
pages = "870--879",
journal = "IEEE Journal on Selected Areas in Communications",
issn = "0733-8716",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - Structured bit-interleaved LDPC codes for MLC flash memory

AU - Haymaker, Kathryn

AU - Kelley, Christine A.

PY - 2014/5

Y1 - 2014/5

N2 - Due to a structural feature in the programming process of MLC (two bits per cell) and TLC (three bits per cell) flash memory, the majority of errors that occur are single-bit errors. Moreover, the voltages used to store the bits typically result in different bit error probabilities for the two or three types of bits. In this work we analyze binary regular LDPC codes in the standard bit-interleaved coded modulation implementation, assuming different probabilities on the bits, to determine what ratio of each type of bit should be connected at the check nodes to improve the decoding threshold. We then propose a construction of nonbinary LDPC codes using their binary images, resulting in check node types that come close to these optimal ratios.

AB - Due to a structural feature in the programming process of MLC (two bits per cell) and TLC (three bits per cell) flash memory, the majority of errors that occur are single-bit errors. Moreover, the voltages used to store the bits typically result in different bit error probabilities for the two or three types of bits. In this work we analyze binary regular LDPC codes in the standard bit-interleaved coded modulation implementation, assuming different probabilities on the bits, to determine what ratio of each type of bit should be connected at the check nodes to improve the decoding threshold. We then propose a construction of nonbinary LDPC codes using their binary images, resulting in check node types that come close to these optimal ratios.

KW - Parity check codes

KW - bipartite graph

KW - iterative decoding

UR - http://www.scopus.com/inward/record.url?scp=84899865885&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84899865885&partnerID=8YFLogxK

U2 - 10.1109/JSAC.2014.140507

DO - 10.1109/JSAC.2014.140507

M3 - Article

AN - SCOPUS:84899865885

VL - 32

SP - 870

EP - 879

JO - IEEE Journal on Selected Areas in Communications

JF - IEEE Journal on Selected Areas in Communications

SN - 0733-8716

IS - 5

M1 - 6804932

ER -