On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms

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3 Citations (Scopus)

Abstract

Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms and proves that this parallelism can always be achieved in hardware system given the availability of a large number of processors and the interconnections between them.

Original languageEnglish (US)
Pages (from-to)106-125
Number of pages20
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume13
Issue number1
DOIs
StatePublished - Jan 1 2005

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Digital signal processing
Availability
Hardware

Keywords

  • Inter-iteration parallelism
  • Multidimensional data flow graph
  • Multidimensional unfolding
  • Multirate signal processing

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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