A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique

Byungseung Lee, Byungill Kim, Juneseok Lee, Sanghoon Hwang, Minkyu Song, Tadeusz A Wysocki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.

Original languageEnglish (US)
Title of host publicationEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
Pages882-885
Number of pages4
DOIs
StatePublished - Aug 25 2008
EventEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007 - Seville, Spain
Duration: Aug 26 2007Aug 30 2007

Publication series

NameEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007

Other

OtherEuropean Conference on Circuit Theory and Design 2007, ECCTD 2007
CountrySpain
CitySeville
Period8/26/078/30/07

Fingerprint

Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Cite this

Lee, B., Kim, B., Lee, J., Hwang, S., Song, M., & Wysocki, T. A. (2008). A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique. In European Conference on Circuit Theory and Design 2007, ECCTD 2007 (pp. 882-885). [4529738] (European Conference on Circuit Theory and Design 2007, ECCTD 2007). https://doi.org/10.1109/ECCTD.2007.4529738

A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique. / Lee, Byungseung; Kim, Byungill; Lee, Juneseok; Hwang, Sanghoon; Song, Minkyu; Wysocki, Tadeusz A.

European Conference on Circuit Theory and Design 2007, ECCTD 2007. 2008. p. 882-885 4529738 (European Conference on Circuit Theory and Design 2007, ECCTD 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, B, Kim, B, Lee, J, Hwang, S, Song, M & Wysocki, TA 2008, A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique. in European Conference on Circuit Theory and Design 2007, ECCTD 2007., 4529738, European Conference on Circuit Theory and Design 2007, ECCTD 2007, pp. 882-885, European Conference on Circuit Theory and Design 2007, ECCTD 2007, Seville, Spain, 8/26/07. https://doi.org/10.1109/ECCTD.2007.4529738
Lee B, Kim B, Lee J, Hwang S, Song M, Wysocki TA. A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique. In European Conference on Circuit Theory and Design 2007, ECCTD 2007. 2008. p. 882-885. 4529738. (European Conference on Circuit Theory and Design 2007, ECCTD 2007). https://doi.org/10.1109/ECCTD.2007.4529738
Lee, Byungseung ; Kim, Byungill ; Lee, Juneseok ; Hwang, Sanghoon ; Song, Minkyu ; Wysocki, Tadeusz A. / A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique. European Conference on Circuit Theory and Design 2007, ECCTD 2007. 2008. pp. 882-885 (European Conference on Circuit Theory and Design 2007, ECCTD 2007).
@inproceedings{8d49fb0dd8584519a3759ca099418e64,
title = "A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique",
abstract = "A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.",
author = "Byungseung Lee and Byungill Kim and Juneseok Lee and Sanghoon Hwang and Minkyu Song and Wysocki, {Tadeusz A}",
year = "2008",
month = "8",
day = "25",
doi = "10.1109/ECCTD.2007.4529738",
language = "English (US)",
isbn = "1424413427",
series = "European Conference on Circuit Theory and Design 2007, ECCTD 2007",
pages = "882--885",
booktitle = "European Conference on Circuit Theory and Design 2007, ECCTD 2007",

}

TY - GEN

T1 - A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique

AU - Lee, Byungseung

AU - Kim, Byungill

AU - Lee, Juneseok

AU - Hwang, Sanghoon

AU - Song, Minkyu

AU - Wysocki, Tadeusz A

PY - 2008/8/25

Y1 - 2008/8/25

N2 - A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.

AB - A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.

UR - http://www.scopus.com/inward/record.url?scp=49749140705&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=49749140705&partnerID=8YFLogxK

U2 - 10.1109/ECCTD.2007.4529738

DO - 10.1109/ECCTD.2007.4529738

M3 - Conference contribution

SN - 1424413427

SN - 9781424413423

T3 - European Conference on Circuit Theory and Design 2007, ECCTD 2007

SP - 882

EP - 885

BT - European Conference on Circuit Theory and Design 2007, ECCTD 2007

ER -